In digital mobile radio communications systems, mobile transmitters must provide relatively high output power in the desired transmission channel, while suppressing powers transmitted in other channels sufficiently to avoid interference with other transmissions, for example with received signals on other nearby mobile transmitters.
In order to ensure as far as possible that these problems are minimised, the standards, such as the GSM standard, set minimum specifications which devices must meet.
At the same time, particularly in the case of portable radio transmitters such as mobile telephones and other handheld devices, there is a desire to minimise the size of the transmitter circuitry and its power consumption, and hence maximise its battery life.
One known technique used in the transmitter circuitry of mobile telephones, is to generate a signal using a voltage controlled oscillator, at a frequency which is a multiple of the desired transmit frequency. This generated signal is then frequency divided down to the desired transmit frequency. This arrangement has the advantage that the physical size of a voltage controlled oscillator, within an integrated circuit, is generally approximately inversely proportional to its output frequency. Therefore, in order to generate an output signal at 1.8 GHz, less silicon area is occupied by a voltage controlled oscillator which produces a signal at 3.6 GHz, followed by a frequency divider which halves that frequency, than would be occupied by a voltage controlled oscillator producing the signal directly at 1.8 GHz.
Moreover, in the case of GSM, two transmit frequency bands are used, one in the region of 1.8 GHz, and one in the region of 900 MHz. Signals in both of these bands can conveniently be generated by a single voltage controlled oscillator producing a signal at 3.6 GHz, followed by a divider, whose division ratio can be set either at two or at four.
The document ‘Completely Integrated 1.5 GHz Direct Conversion Transceiver’ by Weger P et al from the 1994 Symposium on VLSI Circuits Digest of Technical Papers discloses a transceiver that includes a frequency generator and digital divider circuitry for generating signals up to 1.5 GHz. The transceiver also includes a power amplifier for amplifying the generated signal for transmission.
One disadvantage of using this technique for producing the output signals is that the frequency divider introduces a source of noise into the transmit circuitry. As mentioned above, the GSM specification places limits on the permissible noise.
One way of reducing this problem is to operate the frequency divider at low impedance, but this requires a relatively high current to be supplied to the frequency divider, thereby increasing the power consumption of the circuitry.
An alternative solution is to filter the output before it is supplied to the power amplifier, but this increases the overall size of the device, and adds cost.
U.S. Pat. No. 5,894,592 (Brueske et al.) discloses a wideband phase-lock loop frequency synthesiser that includes a divide-by-two divider, a quadrature detector, an offset VCO and offset mixer for generating a quadrature phase modulated signal. A programmable filter is used for removing predetermined harmonic components of the offset mixed signal enabling the synthesiser to operate over a wide frequency range.